Intel(R) Architecture Code Analyzer Version -  v3.0-28-g1ba2cbb build date: 2017-10-23;16:42:45
Analyzed File -  ./GMWC-iaca
Binary Format - 64Bit
Architecture  -  SKL
Analysis Type - Throughput

Throughput Analysis Report
--------------------------
Block Throughput: 4.26 Cycles       Throughput Bottleneck: FrontEnd
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  3.0     0.0  |  3.0  |  1.3     1.0  |  1.4     1.0  |  2.0  |  3.0  |  3.0  |  1.3  |
--------------------------------------------------------------------------------------------------

DV - Divider pipe (on port 0)
D - Data fetch pipe (on ports 2 and 3)
F - Macro Fusion with the previous instruction occurred
* - instruction micro-ops not bound to a port
^ - Micro Fusion occurred
# - ESP Tracking sync uop was issued
@ - SSE instruction followed an AVX256/AVX512 instruction, dozens of cycles penalty is expected
X - instruction not supported, was not accounted in Analysis

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   1      | 1.0         |      |             |             |      |      |      |      | mov rax, 0xff235b1bea19555a
|   2^     |             | 1.0  | 0.6     0.6 | 0.4     0.4 |      |      |      |      | mul qword ptr [rip+0x2ec7]
|   1      |             |      | 0.4     0.4 | 0.6     0.6 |      |      |      |      | mov rcx, qword ptr [rip+0x2ed0]
|   1*     |             |      |             |             |      |      |      |      | mov rsi, rcx
|   1      |             |      |             |             |      |      | 1.0  |      | sar rcx, 0x3f
|   1*     |             |      |             |             |      |      |      |      | mov rdi, rcx
|   1      |             |      |             |             |      | 1.0  |      |      | add rsi, rax
|   1      | 1.0         |      |             |             |      |      |      |      | mov rax, 0xabe68618e06e7101
|   1      |             |      |             |             |      |      | 1.0  |      | adc rdi, rdx
|   1      |             | 1.0  |             |             |      |      |      |      | imul rax, rsi
|   1      |             |      |             |             |      | 1.0  |      |      | mov edx, 0xe38d70ff
|   2^     |             |      |             |             | 1.0  |      |      | 1.0  | mov qword ptr [rip+0x2e96], rax
|   2      |             | 1.0  |             |             |      | 1.0  |      |      | mulx rdx, rax, rax
|   1      | 1.0         |      |             |             |      |      |      |      | add rax, rsi
|   1      |             |      |             |             |      |      | 1.0  |      | adc rdx, rdi
|   2^     |             |      | 0.3         | 0.4         | 1.0  |      |      | 0.3  | mov qword ptr [rip+0x2e94], rdx
Total Num Of Uops: 20